A known configuration of solid-state imaging apparatuses has pixels arranged two dimensionally. Among such solid-state imaging apparatuses, configurations having electronic shutter functions have been known in order to start and finish accumulating signal carriers in all pixels at the same time. The configurations are exemplified in Japanese Patent Application Laid-Open No. 2006-246450 (hereinafter referred to as Patent Document 1) and Japanese Patent Application Laid-Open No. 2006-049743 (hereinafter referred to as Patent Document 2), for example.
For the electronic shutter functions, there are provided, separately from photoelectric conversion portions that perform photoelectrical conversion, carrier holding portions that hold the photoelectrically converted carriers for predetermined time periods.
In the configurations discussed in Patent Document 1 and Patent Document 2, sufficient considerations have not been given in terms of optimizing potential structures within semiconductor substrates by layouts of elements within pixels and disposing light shielding portions for inhibiting light from being incident on carrier holding portions.
The present invention is directed to optimizing a potential structure on a semiconductor substrate in a solid-state imaging apparatus having pixels each including a carrier holding portion, for example, by suitably arranging elements constituting the pixel.